An integrated circuit can contain millions of electrical components such as transistors, resistors, capacitors and diodes, and their associated interconnections, which are usually made through conductive materials comprising deposited metal, polysilicon and the like. An integrated circuit's components and their interconnections are typically arranged in a plurality of layers which are formed over a substrate typically comprising a silicon wafer. Each layer, or common substrate elevation, can contain several thousand conductors. Such conductors are typically electrically insulated from one another by a non-conducting material or dielectric material such as borophosphosilicate glass (BPSG), silicon dioxide, and the like.
Shown in FIG. 1, generally at 20, is a semiconductor wafer fragment comprising a substrate 22, and a plurality of conductors 24, 26, 28, and 30. The conductors are separated from one another, and insulated by dielectric material layers 32, which may or may not comprise the same material. The spacing vertically and laterally of conductors 24-30 can lead to a phenomenon known as parasitic capacitance. Capacitance is a natural phenomenon which exists between any two conductors which are not electrically connected to each other; the closer the proximity of the conductors, the larger the capacitance. Parasitic capacitance is so named because it is an undesirable effect resulting from the very close proximity of conductors in an integrated circuit.
Referring to FIG. 2, conductors 24-30 are shown for clarity without the dielectric layer boundaries. There, some exemplary parasitic capacitances are schematically shown as capacitor elements which are joined between laterally adjacent and overlying conductors. To calculate the parasitic capacitance attributed to an integrated circuit conductor, the capacitance can be broken into components, and modeled as shown in FIG. 2. Three different components of parasitic capacitance are shown and comprise an area capacitance (C.sub.a), a coupling or lateral capacitance (C.sub.c), and a fringing or fringe capacitance (C.sub.f).
The area capacitance, C.sub.a is the component of parasitic capacitance which exists between the top and bottom surfaces of two overlapping conductors. Accordingly, portions of the top surface of conductor 24 are overlapped by portions of the bottom surface of conductor 26. Hence, a parasitic area capacitance can be developed therebetween.
Lateral coupling capacitance, C.sub.c, is the component of parasitic capacitance which exists between adjacent lateral edges of two conductors. Accordingly, the adjacent lateral edges of conductors 26, 28 can give rise to the illustrated coupling capacitance C.sub.c.
Fringing or fringe capacitance, also termed edge capacitance, is the component of parasitic capacitance which exists between a lateral edge of a first conductor, and either the top or bottom surface of a second conductor which overlaps (underlaps) the lateral edge of the first conductor. Accordingly, the leftmost side edge of conductor 26 and the top of conductor 24 can give rise to a fringe capacitance C.sub.f. The fringe capacitance is essentially a distortion to the area capacitance component caused by fringing effects at a conductor's lateral edges. Similarly, there are area and fringe components of capacitance between metals and the semiconductive substrate, as illustrated.
An undesirable effect of parasitic capacitance is to slow the propagation of electrical signals through a circuit, thereby reducing the speed at which an integrated circuit can function. The larger the parasitic capacitance, the greater the delay a signal will encounter as it travels through a conductor. If the parasitic capacitance components of an integrated circuit can be extracted from the integrated circuit's physical design, such components can be used to estimate the delay for each signal in the circuit, through a process known as timing analysis. This information can be used to adjust the physical layout of the conductors in an integrated circuit, thereby optimizing the performance of the integrated circuit.
Typically, within the integrated circuit industry, there are a number of so-called extraction tools, e.g. layout parasitic extractors (LPEs), which are designed to enable circuit designers to extract and analyze such parasitic capacitances. Among these tools are included the Caliber.TM. and xCaliber.TM. physical verification and extraction tools available from Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, Oreg. 97070. Such extraction tools are described in a publication entitled Interconnect Parasitic Extraction for Deep Submicron IC Design, which is available through Mentor Graphics.
In contemporary integrated circuit processing, it is not unusual to employ the use of so-called dummy fill patterns, or fill structures to help in the attainment of process uniformity. Such fill structures are circuit features, such as polysilicon or metal bars, which are deposited and patterned, and may serve no electrical function, but are present in the circuit's topology simply to even out the physical effects in wafer processing steps. As such, they are usually not connected to any circuit node, and are therefore said to be "electrically floating." In contrast to dummy metal, we will refer to the original signal-carrying metal as "active" metal. Exemplary uses of such fill structures are to achieve photolithographic uniformity, etch uniformity, and/or planarization uniformity. That is, when a wafer is planarized, as by chemical-mechanical polishing, such fill structures can facilitate an evenly planarized surface which, in the absence of such fill structure, could dip inwardly or have other non-uniform features.
As an example, FIG. 3 shows the above-described FIG. 1 conductors 24-30, with exemplary fill structures 34, 36, and 38. While the fill structures are useful in providing an enhanced degree of process uniformity, such fill structures can give rise to parasitic electrical effects, such as increasing the parasitic capacitance of the active metal. Such is usually undesirable for all of the reasons set forth above.
For example, FIG. 4 shows conductors 24-30, and fill structures 34-38 with the exemplary parasitic capacitances schematically indicated. With respect to conductor 24, additional parasitic capacitance to other active layers develops due to its coupling capacitance C.sub.c ' to fill structure 34 and fill structure 34's coupling to other active conductors or semiconductors. With respect to conductor 28, parasitic fringe capacitances C.sub.f ', and area capacitance C.sub.a ' develop with fill structure 34. With respect to conductor 30, a parasitic coupling capacitance C.sub.c ' develops with fill structure 36, and fringe capacitances C.sub.f ', and area capacitance C.sub.a ' develop with fill structure 38. Each fill structure in turn has capacitances to other active metal, and the total capacitance of each active metal when calculated according to standard methods familiar to practitioners in the field, is increased relative to the case when there is no dummy metal fill, despite the dummy metal being electrically floating. As mentioned above, these additional parasitic capacitances can give rise to undesirable parasitic effects.
A problem which has arisen with respect to conventionally available layout parasitic extractors (LPEs), is that such extractors do not typically take into account the presence of such fill structures during calibration and extraction of parasitic capacitances. Accordingly, the extracted parasitic capacitances by LPE do not include the increased parasitic effects generated by these fill structures. Accordingly, functional and performance simulations are run based on integrated circuitry structure which does not include the effects of the fill structure. Hence, a level of inaccuracy is injected into the computation of parasitic capacitances, and the evaluation of the subject integrated circuitry.
One reason for the inability to account for the fill structures is that the fill structure pattern is often incorporated into the integrated circuit design as a last step before mask tooling, after the functional and performance simulations and the layout parasitic extraction (LPE). In the normal design flow, the LPE processes the physical layout of the integrated circuit, and based upon a calibrated set of equations or tables, translates the geometric arrangement of metals or conductors into electrical capacitances and resistances, and places them into a circuit simulation input file. If the fill structure pattern does not exist in the physical layout database, then the LPE normally cannot account for its electrical effect. Thus, in the normal design flow, the parasitic capacitive effects of the extra fill structures are not represented in these circuit simulations.
One solution might be to incorporate the fill structure pattern into the design before the LPE and verification simulations. However, it is usually impractical to include as much layout data as the pervasive fill structure pattern would represent in the design database, both from a storage resource standpoint, and, in the run times and run time resources that would be required to perform the usual operations on the database that are part of the normal design flow. It is also a common limitation of present day LPE tools not to be able to accurately extract the effects of floating metal. If one were to connect the floating metal to active nodes, the LPE tool may in principle be able to handle it, but the parasitic capacitances would increase enormously.
Accordingly, this invention arose out of concerns associated with improving the methods and apparatus through which parasitic capacitance values are extracted from physical integrated circuit designs. In particular, this invention arose out of concerns associated with providing methods and apparatus which take into account the parasitic capacitive effects caused by fill structures such as that described above.